For this lab, you will have to implement a positive edge-triggered D Flip Flop using Transmission Gate Logic
Size all the transistors from Lab 1: Part III for
Reference: Transistor Sizing a Complex CMOS Gate from Lecture 6.
In all cases(including minimum W/L), report your observations(Propagation Delays, Rise/Fall times, Power Consumption) with supporting extracted view simulation results.
What you can do before coming to the lab:
1. It
is highly recommended that you go over the Cadence setup and tutorial
pages as you work on this assignment to correctly setup your tool and access.
Follow all steps given under Cadence setup. The documentation provided under
the help menu in each cadence tool also contains detailed information on using
the tools.
2. Go through the lecture that has covered the design
of Complementary CMOS circuits and work on designing the circuit. This saves
you time during the lab session and you have more time to work on your cadence
implementation.
Design a CMOS inverter in Cadence. The width of the NMOS and PMOS transistors should
be 1.5µm and 3µm, respectively. Their lengths can both be set to 0.6µm.
For simulations, set the inverter input signal to have a rise time of 0.5ns, fall
time of 0.5ns, pulse width of 2ns, period of 5ns. Use model files, util/cadence/local/ncsu-cdk-1.6.0.beta-20150506/models/spectre/standalone/ami06N.m
and /util/cadence/local/ncsu-cdk-1.6.0.beta-20150506/models/spectre/standalone/ami06P.m
Propagation Delay (tp):
Propagation delay expresses the delay experienced by a signal when passing
through a gate. tpLH defines the response time of the
gate for a low to high output transition, while tpHL
refers to a high to low transition. The overall propagation delay is
conservatively defined as the average of the two delays tpLH
and tpHL.
You will have to implement the schematic and layout for basic 2-input gates
i.
NAND
ii.
NOR
iii.
XOR
Create symbols
for each schematic.
Useful tips:
1. Another important thing to note is to keep the
width of the PMOS transistors double the width of the NMOS transistors. The width
of the NMOS and PMOS transistors should be 1.5µm and 3µm, respectively. Their
lengths can both be set to 0.6µm.
2. As you have to design 2-input gates, you should test
your circuit for all possible combination of inputs. This can be done using two
pulse inputs, one with twice the time period of the other. Another effective
method to give stimuli is using bit inputs with 0.01ns rise and fall times.
Implement the given logic function using CMOS logic
(Transistor level diagram).
F = ^[((AB)+C)D]
Size all transistors with their minimum
default W/L